In the case of conventional memory devices, in particular conventional semiconductor memory devices, one differentiates between so-called functional memory devices (e.g. PLAs, PALs, etc.), and so-called table memory devices, e.g. ROM devices (ROM=Read Only Memory)—in particular PROMs, EPROMs, EEPROMs, flash memories, etc. —, and RAM devices (RAM=Random Access Memory or read-write memory), e.g. DRAMs and SRAMs.
A RAM device is a memory for storing data under a predetermined address and for reading out the data under this address again later.
Since as many memory cells as possible are to be accommodated in a RAM device, one has been trying to realize them as simple as possible.
In the case of SRAMs (SRAM=Static Random Access Memory), the individual memory cells consist e.g. of few, for instance 6, transistors, and in the case of so-called DRAMs (DRAM=Dynamic Random Access Memory) in general only of one single, correspondingly controlled capacitive element (e.g. a trench capacitor) with the capacitance of which one bit each can be stored as charge.
This charge, however, remains for a short time only. Therefore, a so-called “refresh” must be performed regularly, e.g. approximately every 64 ms.
In contrast to that, no “refresh” has to be performed in the case of SRAMs, i.e. the data stored in the memory cell remain stored as long as an appropriate supply voltage is fed to the SRAM.
In the case of non-volatile memory devices (NVMs), e.g. EPROMs, EEPROMs, flash memories, OTPs, etc., the stored data remain, however, stored even when the supply voltage is switched off.
The memory cells provided in the above-mentioned memory devices are each adapted to be connected to corresponding bit lines so as to transmit a data value to be read out from a memory cell or a data value to be read in to a memory cell.
On reading out a memory cell, an access transistor connected with a memory cell is first of all connected through by the activation or selection, respectively, of a word line, and the charge state stored in the memory cell is applied to the bit line. Later, the weak signal coming from the memory cell is amplified by a sense amplifier, or evaluated by an evaluator circuit, respectively.
Prior to the reading out of the memory cell, the corresponding bit line is precharged to a predetermined potential by a so-called precharge circuit that is connected with the corresponding bit line.
If a corresponding bit line is selected or activated, respectively, the parasitic capacitances thereof will first of all have to be charged. The corresponding charging current may, for instance, be provided by the above-mentioned precharge circuit and by further transistors that are connected between the bit line and the supply voltage.
The charging current results in a relatively high voltage drop at a node positioned between the above-mentioned evaluator circuit and the bit line. Before the evaluator circuit evaluates the charging current of the memory cell, the voltage at this node first has to achieve a predetermined target value. The result of this is relatively long access times.
For this and other reasons there is a need for the present invention.